Abolfazl Sajadi

Digital Hardware Engineer · Hardware Security

TAPED OUT — GF 22FDX

Digital hardware engineer completing a PhD at Leiden University, with hands-on experience in RTL/SoC design, RISC-V integration, FPGA prototyping, ASIC implementation, and hardware security. Experienced in taking digital systems from RTL and verification through physical implementation and tape-out.

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Portrait of Abolfazl Sajadi
Abolfazl “Abish” Sajadi Leiden University (LIACS)

About

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I'm a digital hardware engineer completing my PhD at LIACS, Leiden University, working on hardware security and digital IC design in the PROACT project. I designed the full PROACT dual-core RISC-V cryptographic SoC — the RTL architecture, full-chip integration and all peripheral & control logic (SPI, a configurable UART, control/status registers and a PRNG) — integrating third-party IP such as the Ibex RISC-V core and the AES, Ascon and Xoodyak cryptographic co-processors, first prototyping on Xilinx FPGAs and then taking the design to a 22 nm ASIC: synthesis in Cadence Genus for GlobalFoundries 22FDX, functional and gate-level verification in Xcelium, and place-and-route and sign-off with the imec team, through to tape-out.

I also developed the chip's software stack — C and Python libraries and a control GUI — and its documentation, and designed a ChipWhisperer CW308 target board in Altium with an automated CPA/TVLA side-channel flow. I'm strongest in the front-end (RTL design, synthesis, functional verification), with hands-on FPGA prototyping, software and side-channel board experience.

Career & Education

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FIG. 1 — CAREER & EDUCATION TIMING DIAGRAM, 2011–2027 · drag sideways to see the full diagram

Experience

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AUG 2022 – FEB 2027 · ONGOING

Doctoral Researcher — Digital IC & Hardware Security

Leiden University (LIACS) · Leiden, NL

  • Designed the full PROACT dual-core RISC-V cryptographic SoC — RTL architecture, full-chip integration and all peripheral & control logic (SPI, configurable UART, control/status registers, PRNG) — integrating the Ibex core and the AES, Ascon and Xoodyak co-processors as third-party/partner IP, from RTL to full chip.
  • Prototyped and validated the SoC on Xilinx Artix-7 and Zynq-7000 FPGAs using SPI/UART interfaces; developed C and Python libraries, a control GUI, and user documentation.
  • Synthesized the SoC for GlobalFoundries 22FDX using Cadence Genus and performed functional and SDF-annotated gate-level verification in Xcelium.
  • Contributed to ASIC physical implementation and MPW tape-out with the imec team, including place-and-route, sign-off, GDSII generation, and design of the 28-pin DIP package bonding diagram.
  • Built a ChipWhisperer CW308 target board (Altium) and automated CPA/TVLA side-channel evaluation of AES on the RISC-V core.

2018 – 2021

M.Sc. + Research Assistant — Digital Electronic Systems

University of Tehran (DVD-ES Lab) · Tehran, IR

  • M.Sc. (GPA 18.28/20, ranked 1st) alongside full-time research at the DVD-ES Lab: designed and evaluated ML-resistant PUF authentication protocols (DC-PUF, SQ-PUF) on FPGA and implemented CNN/SVM modeling attacks in Python (published in J. Network & Computer Applications).

2020 – 2021

Hardware Engineer

Ryan iMachines

  • ML-algorithm design, RTL (Verilog) implementation, test and debug.

2020

Hardware Engineer (project-based)

Shahab Co.

  • Home Meter Monitoring Device: ESP32 + AVR (ATmega8) firmware and a custom PCB designed in Altium — see project card.

EARLIER

Private tutor, VHDL & FPGA — OstadSalam.ir (2020–21) · Web designer — ETC Co. (2019), four commercial WordPress sites

The PROACT Chip

req

A hardware-security research SoC taken from RTL to a fabricated 22 nm ASIC — dual 32-bit RISC-V architecture: a controller core plus an Ibex software-executor core, with AES, Ascon and Xoodyak crypto co-processors.

2.009 × 2.055 mm²die, incl. scribe
GF 22FDX22 nm process
Europractice MPW50 packaged units
Taped outfabrication in progress

// my role

  • Full-chip design & integration: RTL architecture, full-chip integration and all peripheral & control logic (SPI bridge, configurable UART, control/status registers, PRNG) — integrating the Ibex core and the AES, Ascon and Xoodyak co-processors as third-party IP.
  • FPGA prototyping: ZYBO and PYNQ-Z2 boards.
  • Software stack: C/Python libraries, control GUI, and documentation.
// asic flow & side-channel platform
  • Synthesis in Cadence Genus for GlobalFoundries 22FDX; functional and SDF-annotated gate-level verification in Xcelium.
  • Place-and-route, sign-off and GDSII with the imec team; 28-pin ceramic DIP bonding diagram.
  • Custom ChipWhisperer CW308 target board (Altium, 4-layer, 0.01 Ω shunt) with an automated CPA/TVLA evaluation flow.
Stylized floorplan of the PROACT test chip — 2.009 × 2.055 mm² die in GlobalFoundries 22FDX. I designed the full SoC — the RTL architecture, full-chip integration and all peripheral & control logic (SPI, UART, CSR, PRNG, amber) — integrating third-party IP such as the Ibex RISC-V core and the AES, Ascon and Xoodyak cryptographic co-processors (grey), from RTL through FPGA prototyping to tape-out.
  • Peripheral & control RTL I designed — SPI, UART, CSR, PRNG
  • Integrated IP — Ibex RISC-V core, AES/Ascon/Xoodyak co-processors

Selected Projects

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PYTHON / PYTORCH GEOMETRIC

FLASH-Trace — GNN pre-silicon power-trace generation

A spatiotemporal Graph Neural Network (GCN + dilated TCN) that predicts gate-level power traces up to 9× faster than Cadence Joules, accurately enough for full AES-128 key recovery by CPA. First-author paper under submission to IACR TCHES.

OPEN-SOURCE / ACM CF'26

ASSESS — pre-silicon side-channel leakage analysis

A cycle-accurate methodology that localizes gate-level side-channel leakage from toggle activity, fast enough for routine checks during iterative ASIC design; benchmarked against RTL-PAT, PATCH and ACA on RISC-V/AES designs.

VIVADO HLS / B.SC. THESIS

Real-time object detection & tracking on Zynq-7000

Real-time object detection and tracking on a ZYBO Zynq-7000 — HDMI video in, colour-range filtering, and distance estimation from object size, with simultaneous LED-matrix and VGA output plus UART telemetry. Verified in MATLAB/OpenCV, then synthesized to hardware with HLS + Vivado.

Real-time object detection & tracking system on a ZYBO Zynq-7000: camera and HDMI input, color-based detection, LED-matrix and VGA output

View B.Sc. thesis demos

RTL / QUARTUS / CYCLONE II

CNN accelerator on FPGA

RTL implementation of a tiny convolutional-network accelerator (MNIST), validated against a Keras reference model and brought up on an Altera Cyclone II board.

ESP32 / AVR / ALTIUM · 2020

Home meter monitoring device

Design & implementation of a Home Meter Monitoring Device — project-based (Arduino, AVR, PCB). Implemented on ESP32 and AVR (ATmega8) microcontrollers, with a custom PCB designed in Altium Designer (2020). Delivered for Shahab Co.

Three custom ESP32-CAM-based monitoring PCBs designed in Altium

Publications

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  5. UNDER SUBMISSION

    FLASH-Trace: Fast & Learning-based Pre-Silicon Power Trace Generation with GNNs

    A. Sajadi, S. Shiri, N. Zidarič, T. Stefanov, N. Mentens

    IACR TCHES — in review

// full list on Google Scholar

Education

valid

AUG 2022 – FEB 2027 · ONGOING

Ph.D. in Computer Science

Leiden University (LIACS), NL

Hardware security & digital IC design (PROACT). Dissertation: pre/post-silicon side-channel leakage evaluation in lightweight cryptographic circuits.

Thesis details →

2018 – 2021 · GPA 18.28/20

M.Sc. in Electrical Engineering — Digital Electronic Systems

University of Tehran · Ranked 1st in class

Thesis: ML-based modeling attacks on Physical Unclonable Functions (PUFs). Completed alongside a full-time research assistantship at the DVD-ES Lab.

Thesis details →

2014 – 2017 · GPA 16.87/20

B.Sc. in Electrical Engineering — Electronic Technology

Mohajer Technical University (MTU), Isfahan · Ranked 1st in the class of 2014

Thesis: real-time object detection & tracking on a Zynq-7000 SoC.

Thesis details →

2011 – 2013 · FULL SCHOLARSHIP

Associate Degree in Electronics

Amirkabir Technical & Vocational University of Markazi, Arak

Thesis: three-phase pure sine inverter — analog design with adjustable frequency, phase and amplitude.

Thesis details →

Theses

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PH.D.ONGOING

Pre/Post-Silicon Evaluation of Side-Channel Leakage in Lightweight Cryptographic Circuits

Leiden University (LIACS) · 2022 – 2027 (expected)

Pre- and post-silicon side-channel leakage evaluation across the PROACT SoC, ASSESS and FLASH-Trace.

M.SC.2021 · Grade: Excellent

Implementation of Machine-Learning-based Attacks on PUF

University of Tehran

ML modeling attacks on RPUF and OBPUF, and SQ-PUF — a secure, scalable, ML-attack-resistant architecture.

B.SC.2016 · 19.75/20

Detection and Tracking of Moving Objects on the ZYNQ Platform

Mohajer Technical University of Isfahan

Real-time HDMI-in object detection and tracking on Zynq-7000, from MATLAB and OpenCV to HLS on silicon.

ASSOCIATE2013

Three-phase Pure Sine Inverter

Amirkabir Technical & Vocational University, Arak

Analog three-phase pure-sine inverter with adjustable frequency, phase and amplitude at 220 V output.

Honors & Awards

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  • 2020

    Ranked 1st in class (Digital Electronic Systems, cumulative GPA) · University of Tehran

  • 2018

    Ranked 102nd of 30,000+ · Iran nationwide M.Sc. entrance exam (electronics)

  • 2017

    Ranked 1st in the class of 2014 (cumulative GPA) · Mohajer Technical University

  • 2014

    Top 1% · nationwide Associate-to-Bachelor entrance exam (TVU)

  • 2013

    1st place, provincial stage · 14th National Skills Competition (WorldSkills, electronics)

  • 2012

    3rd place, provincial stage · National Scientific-Practical Competition (electronics)

  • 2010

    Diligent Student Award · Bozorgmehr Technical & Vocational School

LANGUAGES Persian (native) · English (professional working) · Dutch (A2)

Certifications & Badges

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Genus Physical Synthesis Flow v23.1

Cadence · 2024

verify on credly ↗

Artificial Intelligence & Machine Learning Fundamentals v1.0

Cadence · 2025

verify on credly ↗

Semiconductor 101 v1.0

Cadence · 2024

verify on credly ↗

Tcl Scripting for EDA v8.6

Cadence · 2025

download certificate (pdf) ↓

Cadence RTL-to-GDSII Flow v6.0

Cadence · 2025

download certificate (pdf) ↓

Technical Skills

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HARDWARE LANGUAGES
  • VHDL
  • Verilog
  • SystemVerilog
  • High-Level Synthesis (HLS)
PROGRAMMING
  • Python
  • C/C++
  • Tcl (EDA scripting)
ASIC FRONT-END
  • RTL design
  • RISC-V (Ibex) integration
  • Logic synthesis
  • SDC constraints
  • STA
  • Gate-level simulation
BACK-END
  • Place-and-route
  • Sign-off
  • GDSII
  • Bonding diagram (GF 22FDX)
VERIFICATION
  • RTL testbenches
  • Functional simulation
  • SDF-annotated gate-level simulation
  • FPGA validation
  • Hardware debugging
FPGA & EMBEDDED
  • Xilinx FPGAs
  • Vivado & Vivado HLS
  • Catapult HLS
  • SPI/UART
  • ESP32
  • AVR
HARDWARE SECURITY
  • CPA
  • DPA
  • TVLA
  • SNR/NICV
  • ChipWhisperer
  • Pre-silicon leakage analysis
  • PUFs
DESIGN METHODS
  • HW/SW co-design
  • Continuous integration (CI)
  • Design-for-test (DfT)
  • Fault-tolerant design
ML & EDA
  • Cadence (Genus, Joules, Xcelium)
  • Altium
  • MATLAB
  • PyTorch
  • PyTorch Geometric
  • scikit-learn
  • Keras
PARALLEL COMPUTING
  • CUDA
  • OpenMP
  • POSIX threads
  • SIMD

Teaching, Supervision & Activities

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Teaching
  • Teaching Assistant, System & Software Security, Leiden University (2022–present).
  • Earlier TA experience at the University of Tehran (2019–2022), including Chief TA for Core-based Embedded System Design and earlier TA courses.
Student supervision
  • Co-supervised 6+ B.Sc. theses on AES/RISC-V side-channel analysis and chip-prototype leakage assessment. Completed:
    • Imke van Ooijen — “Optimizing AES for RISC-V Cores” (2024)
    • Niels de Wit — “Power Leakage of AES Implementations” (2024)
    • Lennart van Drunick — “On the Vulnerabilities of FPGAs to Power Hammering Circuits” (2026)
    • Nathanael Mohanu — “Side-Channel Analysis of the PROACT Chip Prototype” (2026)
    • and further B.Sc. theses in progress.
Academic service
  • Reviewer, IEEE Transactions on Computer-Aided Design (TCAD).
Summer & training schools
  • CPS Summer School 2023 (Sardinia).
  • Real-World Crypto & Privacy 2023 (Croatia).
  • PROACT Hardware-Security Training Schools (2023, 2025).

Contact

done

Open to roles in RTL/SoC design, HW/SW co-design, FPGA prototyping, ASIC physical design, or cryptographic hardware.

EMAIL a.sajadi@liacs.leidenuniv.nl PHONE +31 6 81183983 LINKEDIN linkedin.com/in/abisj GITHUB github.com/abolfazlsajadi ORCID 0000-0003-0657-7022 GOOGLE SCHOLAR Profile LEIDEN UNIVERSITY Staff page DOWNLOAD CV (PDF, 2 pages)