The PROACT test chip — taped out in GlobalFoundries 22FDX
Fabrication in progress — post-silicon side-channel evaluation is the next phase of this thesis.
Pre/Post-Silicon Evaluation of Side-Channel Leakage in Lightweight Cryptographic Circuits
Leiden University (LIACS) · Aug 2022 – Feb 2027 (expected) · PROACT project
Work in progress. This doctorate is ongoing: the title above is tentative and the defence is expected in February 2027. Everything below describes results achieved so far.
- TITLE (TENTATIVE)
- Pre/Post-Silicon Evaluation of Side-Channel Leakage in Lightweight Cryptographic Circuits
- DEGREE
- Ph.D. in Computer Science — ongoing
- UNIVERSITY
- Leiden University (LIACS), Leiden, The Netherlands
- PERIOD
- Aug 2022 – Feb 2027 (expected defence)
- SUPERVISORS
- Prof. Nele Mentens · Dr. Todor Stefanov · Dr. Nuša Zidarič
- PROJECT
- PROACT — NWO NWA Cybersecurity programme, grant NWA.1215.18.014 (PI: Prof. Nele Mentens)
Overview
My doctorate sits at the intersection of hardware security and digital IC design, inside the PROACT project (opens in a new tab). The central question: how can the side-channel leakage of cryptographic hardware be evaluated before the chip exists — at design time, from simulation data — and how well do those pre-silicon estimates hold up against measurements on real silicon?
The silicon half of the answer is the PROACT test chip, a dual-core RISC-V cryptographic SoC. I designed the full SoC — the RTL architecture, full-chip integration and all peripheral & control logic (SPI, a configurable UART, control/status registers and a PRNG) — integrating third-party IP such as the Ibex RISC-V core and the AES, Ascon and Xoodyak cryptographic co-processors, which were developed by project partners. I prototyped the SoC on Xilinx FPGAs, developed its C and Python libraries, control GUI and documentation, synthesized it for GlobalFoundries 22FDX in Cadence Genus, verified it in Xcelium, and completed place-and-route and sign-off with the imec team, through to tape-out.
The pre-silicon half is a pair of analysis methods: ASSESS, a cycle-accurate methodology that localizes gate-level side-channel leakage from toggle activity fast enough for routine use during iterative ASIC design, and FLASH-Trace, a graph-neural-network approach that generates gate-level power traces much faster than commercial power simulation while staying accurate enough for key-recovery attacks. Both are described on the projects section of the main page.
Post-silicon evaluation is planned once the fabricated chip is delivered: a custom ChipWhisperer CW308 target board and an automated CPA/TVLA measurement flow are already in place, so pre-silicon predictions can be compared directly against physical measurements of the same design.
Contributions so far
- PROACT SoC — full-chip design & integration: designed the full dual-core RISC-V SoC — the RTL architecture, full-chip integration and all peripheral & control logic (SPI, configurable UART, control/status registers, PRNG) — integrating the Ibex core and the AES, Ascon and Xoodyak co-processors as third-party IP; prototyped on Xilinx Artix-7 and Zynq-7000 FPGAs.
- Software stack & documentation: C and Python control libraries, a control GUI, and user documentation for the chip.
- ASIC implementation: synthesis for GlobalFoundries 22FDX in Cadence Genus, functional and SDF-annotated gate-level verification in Xcelium; place-and-route, sign-off and GDSII with the imec team, including the 28-pin DIP bonding diagram — taped out via a Europractice MPW (50 packaged units).
- ASSESS: a cycle-accurate pre-silicon leakage-analysis methodology that localizes gate-level leakage from toggle activity, benchmarked against RTL-PAT, PATCH and ACA on RISC-V/AES designs (ACM CF Companion '26).
- FLASH-Trace: a spatiotemporal GNN (GCN + dilated TCN) that predicts gate-level power traces up to 9× faster than Cadence Joules, accurate enough for full AES-128 key recovery by CPA (first-author paper under submission to IACR TCHES).
- Countermeasure studies: a systematic comparison of side-channel countermeasures for RISC-V-based SoCs (IEEE NorCAS 2024) and a security/cost trade-off study of AES software countermeasures (ACM CF '26 poster).
- Measurement platform: a ChipWhisperer CW308 target board designed in Altium with an automated CPA/TVLA side-channel evaluation flow, ready for the post-silicon phase.
Methods & technologies
Outcomes & publications
-
-
Systematic Comparison and Improvement of Pre-silicon Leakage Analysis Tools (opens in a new tab)
ACM Computing Frontiers (CF Companion '26), 2026 · DOI 10.1145/3801488.3807896
-
A Systematic Comparison of Side-channel Countermeasures for RISC-V-based SoCs (opens in a new tab)
IEEE NorCAS, 2024 · DOI 10.1109/NorCAS64408.2024.10752477
-
Security and Cost Trade-offs of Side-Channel Countermeasures for AES Software on RISC-V SoCs (opens in a new tab)
ACM CF '26, 2026 · DOI 10.1145/3801487.3805609
-
FLASH-Trace: Fast & Learning-based Pre-Silicon Power Trace Generation with GNNs
IACR TCHES — in review
// full list on the publications section of the main page